The present invention generally relates to a method for manufacturing a high-integrated semiconductor apparatus, and more specifically, to a method for manufacturing a semiconductor apparatus with plural transistors such as a saddle-fin transistor and a multi-channel transistor.
A dynamic random access memory (DRAM) as a representative example of semiconductor apparatus includes a plurality of unit cells each including a capacitor and a transistor. A capacitor is used to temporarily store data, and a transistor is used to transmit data between a bit line and the capacitor in response to a control signal (word line) using a semiconductor property that is the electric conductivity changing depending on environment. The transistor includes a gate, a source and a drain, and charges move between the source and the drain in response to the control signal inputted into the gate. The movement of charges between the source and the drain is performed through a channel region using the semiconductor property. The source and the drain have first ends connected to a bit line, and second ends connected to the capacitor.
Due to increase in the data capacity and integration of the semiconductor memory apparatus, the size of each unit cell is required to be smaller. That is, the design rule of the capacitor and the transistor included in the unit cell is decreased, so that the channel length of the cell transistor is reduced to cause a short channel effect and a drain induced barrier lower (DIBL) effect in the transistor. Moreover, the junction resistance is increased by reduction of the junction area to reduce a driving current of the transistor, thereby degrading the reliability of the operation. By using a three-dimensional cell transistor, it is possible to secure the channel length of the cell transistor in a vertical direction although the design rule is reduced. When the channel length of the cell transistor is secured, the doping concentration in the channel region can be reduced, thereby preventing degradation of a refresh characteristic. Furthermore, in order to increase a driving current in the three-dimensional cell transistor, a saddle-fin transistor has been used.